Job Description

Senior Analog/Mixed Signal ASIC Design Engineer Direct Hire FTE 40 hours weekly, Hybrid role TBD at hire Must be a US Citizen and be clearable to obtain a security clearance. Full Benefits including full relocation for out of area candidates. Job Description Summary: We are seeking a Senior Analog/Mixed Signal ASIC Design Engineer to join our team in the Silicon Architecture group. Members of our group lead the design of integrated circuits from conceptual phases through detailed design, implementation, verification, test and delivery to our customers. Designers in the Silicon Architecture group are responsible for developing initial architectural concepts and vetting them through modeling, analysis, and simulation. We work with both Analog and Digital Circuit Designers to identify opportunities for trades across domains which enable the most efficient design solution. We are involved in the full design lifecycle and often take chip-lead roles on our projects. Typical responsibilities include creating top level and circuit-level specifications, developing conceptual circuit designs, reviewing detailed block-level designs during implementation, conducting chip level-planning with implementation team, and providing inputs to verification and test planning. Job Description: Duties/Responsibilities Design and simulate circuits at transistor-level to implement architecture and requirement specifications Contribute to system-level design Optimize hardware designs for performance, power, and cost Evaluate the hardware feasibility of complex algorithms and requirements Independently contribute to complex chip architectures and designs Independently drive solutions to complex problems - develop requirements, propose ways forward when customer requirements are unclear or incomplete, and adapt appropriately to changes in requirements Contribute to business development and proposal activities Develop, document, and teach best practices to less experienced engineers Perform or guide physical layout, including floor-planning, and simulate circuits using extracted parasitics. Perform other duties as assigned Skills/Abilities Proficiency in integrated circuit design Understanding of integrated circuits, semiconductors, and general computer architecture Ability to write detailed design specifications Ability to manage small technical teams Excellent verbal and written communication skills Excellent mathematical skills Excellent organizational skills and attention to detail Excellent time management skills with the proven ability to meet deadlines Strong analytical and problem-solving skills Ability to prioritize tasks Demonstrate strong organization, planning, and time management skills to achieve program goals Education Requires a bachelor's degree in Engineering, or related field. Masters degree preferred. Requires 5-7 years of experience with a bachelor's degree, or 3-5 years of experience with a master's degree, or 0-2 years of experience with a PhD in ASIC Hardware Engineering or related Experience Requires 5-7 years of experience with a bachelor's degree, or 3-5 years of experience with a master's degree, or 0-2 years of experience with a PhD in ASIC Hardware Engineering or related. Additional Job Description: Additional Responsibilities: • Develop chip-level and block-level integrated circuit requirements based on customer needs. • Design and simulate circuits using functional modeling tools (e.g. MATLAB, Simulink, System Verilog) • Lead multidisciplinary design teams, providing clear and effective communication to the team and project manager. • Participate in technical project planning and provide technical inputs to business development activities. Preferred Qualifications: • Proficiency with Cadence Virtuoso or equivalent mixed signal integrated circuit design tools • Expertise in high level mixed-signal modeling & verification tools such as System Verilog, SV-RNM, Verilog-AMS • Proficient in scripting (e.g. Python, SKILL) for automating aspects of the design, implementation, verification, and test flows. • Experience in top level design for previous tape outs

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